The present invention relates in general to telecommunication systems and components therefor, and is particularly directed to a new and improved, reduced complexity switchmode power converter for controlling the voltage supplied to a subscriber line interface circuit in accordance with the sensed line voltage.
In order to convey digital telecommunication signals over a traditional (plain old telephone service or POTS) telephone line, it is necessary to provide an interface between the source of the digital signals and the analog telephone line. This interface, customarily termed a subscriber line interface circuit or SLIC, is generally configured of one or more integrated circuits that support a number of functions including battery feed, overvoltage protection, ringing, supervision, hybrid and test (BORSHT). When a POTS phone is off-hook, the SLIC must be powered with a voltage that is high enough to ensure that the required DC loop current (typically on the order of 18-50 mA), upon which the voice signal is superimposed, is generated for maximum loop resistance (longest line). While this can be accomplished in a brute force manner by setting the voltage to a value based upon a maximum length line, doing so wastes power for a short line length application.
For example, supplying a loop current of 25 mA through a line having 1000 ohms total line resistance to a 500 ohm phone requires a minimum of 37.5 VDC at the line interface. A short line, on the other hand, operating at the same voltage (37.5 VDC) will waste power by dropping the excess voltage across the SLIC. In this example, for a reduced line resistance of only 100 ohms, over 500 mW of power would be needlessly dissipated in the SLIC circuitry. In order to reduce power consumption for short lines, vendors of SLIC ICs typically offer an IC with two power inputs. One is for use with a high voltage supply, the other for use with a low voltage supply. The SLIC automatically determines which supply rail to use depending on line conditions. Power is reduced for short line lengths by powering the line from the lower voltage source.
Pursuant to the present invention, this power consumption problem is substantially diminished by monitoring the line voltage, and using a reduced complexity switchmode power converter to control the voltage supplied to and therefore the voltage drop across the SLIC, so that the voltage applied to the SLIC""s power terminals is slightly higher than the sensed voltage. The voltage margin or headroom across the SLIC is dependent upon the specifics of the SLIC circuitry and is typically on the order of 2-15 V. In accordance with a non-limiting, preferred embodiment, the reduced complexity switchmode power converter of the present invention is configured to provide power supply tracking during the SLIC""s application of loop current and superimposed voice to the loop, and also during loop start, ground start and balanced ringing.
For this purpose, a comparator, which effectively functions as a pulse width modulator of the conductivity path through a MOSFET installed in the power supply rail to the SLIC, has a first input terminal coupled through a voltage divider to a xe2x80x98DC-DC outputxe2x80x99 node, downstream of a MOSFET switch installed in a (xe2x88x9248V) DC supply rail. The comparator has a second input terminal coupled through a voltage divider to a xe2x80x98set pointxe2x80x99 or reference node. The DC-DC output node is coupled through a post LC filter to the (xe2x88x92) DC power supply terminal of the SLIC. The set point node is coupled through a Zener diode and a buffer transistor to diodes that connect to the tip and ring lines of the loop, and thereby provide for tracking of the most negative of the tip and ring portions of the loop. The buffer transistor reduces loading on tip and ring and also removes the effect of the voltage drop through either diode. The Zener diode provides a prescribed DC voltage offset (e.g., xe2x88x925V) between the set point node and the most negative of tip and ring, to give the SLIC headroom to operate.
The output of the comparator is coupled to the control gate of a MOSFET, having its source-drain path coupled in circuit with the DC power supply rail and an LC smoothing filter to the DC-DC output node. The comparator turns on the MOSFET and thereby couples the DC supply rail through the LC filter paths to the SLIC, when the DC-DC output node is less negative than the voltage at the set point node. In a complementary manner, when the DC-DC output node is more negative than the voltage at the set point node, the comparator turns the MOSFET off, and thereby decouples the supply rail from the LC filter paths to the SLIC.